Abstract
An efficient hardware algorithm for the conversion of an integer X to its residue modulo a predefined integer m, is introduced. The algorithm is based on successive subtractions of appropriately selected multiples of m, from the input X, and it leads to fast evaluation of the residue, via hardware of low complexity. A VLSI architecture for the implementation of the algorithm is also proposed.
| Original language | British English |
|---|---|
| Pages (from-to) | 671-680 |
| Number of pages | 10 |
| Journal | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation |
| State | Published - 1999 |
| Event | 1999 IEEE Workshop on SiGNAL Processing Systems (SiPS 99): 'Design and Implementation' - Taipei, Taiwan Duration: 20 Oct 1999 → 22 Oct 1999 |