@inproceedings{78bfb817805f4ba1a87c38ab39225b3a,
title = "Novel fast and scalable parallel union-find ASIC implementation for real-time digital image segmentation",
abstract = "This paper presents a new fast and scalable Parallel Union-Find algorithm for image segmentation and its System-on-Chip (SoC) implementation using 65nm CMOS technology following the Application-Specific Integrated Circuit (ASIC) design flow. The algorithm is capable of labeling all foreground and background pixels, using the least possible pixels scanning. This contrasts the classical labeling algorithms that label only foreground (or background) pixels in a single run. The new algorithm utilizes only two memory blocks. In one memory block, it labels image segments using their seeds as the label and, simultaneously, the segments sizes are used as the other label in second memory block. By this parallel labeling, monitoring the image segments is very fast and efficient. With 350 MHz operating frequency, the processing rate estimated to be 2100 frames/sec, the total chip area of 15950.5 μm2 (off-chip memory) and very low-power of 0.3 mW, the SoC tends to be an excellent candidate for mobile devices and real-time applications.",
keywords = "ASIC, Low-power, Parallel Labeling, Real-time, Segmentation, SoC, Union-Find Algorithm",
author = "Ehab Salahat and Hani Saleh and Andrzej Sluzek and Mahmoud Al-Qutayri and Baker Mohammad and Mohammad Ismail",
note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; 41st Annual Conference of the IEEE Industrial Electronics Society, IECON 2015 ; Conference date: 09-11-2015 Through 12-11-2015",
year = "2015",
doi = "10.1109/IECON.2015.7392579",
language = "British English",
series = "IECON 2015 - 41st Annual Conference of the IEEE Industrial Electronics Society",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "3122--3125",
booktitle = "IECON 2015 - 41st Annual Conference of the IEEE Industrial Electronics Society",
address = "United States",
}