TY - JOUR

T1 - Multiple-valued logic voltage-mode storage circuits based on true-single-phase clocked logic

AU - Thoidis, I.

AU - Soudris, D.

AU - Karafyllidis, I.

AU - Thanailakis, A.

AU - Stouraitis, T.

PY - 1998

Y1 - 1998

N2 - A number of novel voltage-mode multiple-valued logic circuits are introduced. Adopting the main features of the true single-phase clocked logic, efficient quaternary logic dynamic and pseudo-static latches, dynamic and static master-slave storage units, and uni-signal controlled pass gates are proposed. These circuits use two kinds of MOS transistors, i.e., enhancement and depletion mode, each of which has two threshold voltages. The proposed circuits exhibit regular, modular, and iterative structure, which means that the MVL circuits are VLSI implementable and can be easily re-designed for any radix of an arithmetic system. Since we use only clock signal, the derived circuits have low power dissipation. Comparisons with existing circuits prove substantial improvements in terms of speed, power consumption, and transistor count.

AB - A number of novel voltage-mode multiple-valued logic circuits are introduced. Adopting the main features of the true single-phase clocked logic, efficient quaternary logic dynamic and pseudo-static latches, dynamic and static master-slave storage units, and uni-signal controlled pass gates are proposed. These circuits use two kinds of MOS transistors, i.e., enhancement and depletion mode, each of which has two threshold voltages. The proposed circuits exhibit regular, modular, and iterative structure, which means that the MVL circuits are VLSI implementable and can be easily re-designed for any radix of an arithmetic system. Since we use only clock signal, the derived circuits have low power dissipation. Comparisons with existing circuits prove substantial improvements in terms of speed, power consumption, and transistor count.

UR - http://www.scopus.com/inward/record.url?scp=0031703450&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:0031703450

SN - 1066-1395

SP - 83

EP - 88

JO - Proceedings of the IEEE Great Lakes Symposium on VLSI

JF - Proceedings of the IEEE Great Lakes Symposium on VLSI

T2 - Proceedings of the 1998 8th Great Lakes Symposium on VLSI

Y2 - 19 February 1998 through 21 February 1998

ER -