Multifunction architectures for RNS processors

Novel very large-scale integration architectures and a design methodology for adder-based residue number system (RNS) processors are presented in this paper. The new architectures compute residues for more than one modulus either serially or in parallel, while their use can increase the resource utilization in a processor. Complexity is reduced by sharing common intermediate results among the various RNS moduli channels and/or operations that compose an RNS processor. The presented architectures are distinguished into two subtypes, depending on whether the inter-channel parallelism is preserved or not. The multifunction architecture paradigm is demonstrated by its application in residue multiplication, binary-to-residue conversion, quadratic RNS (QRNS) mapping, and base extension. The derived architectures are compared to previously reported equivalent ones and are found to be efficient in area × time product sense. Finally, the proposed design methodology reveals a new tradeoff in residue processor design, leading to more efficient RNS processors.