Methodology for the design of signed-digit DSP processors

A generalized systematic graph-based methodology for designing novel architectures based on Signed-Digit representation, is introduced. The proposed methodology starts from the algorithmic level and ends up with the implementation at the digit level. Taking into account the target architecture, the dependence graph of the algorithm is described by a set of Uniform Recurrent Equations. Depending on the target architecture, regular or tree array architectures are derived, which demonstrate low latency and high throughput rates. Several designs are presented, that exhibit regularity, modularity, and local interconnections, being amenable for VLSI implementation. The introduced methodology is demonstrated by the design of an array multiplier.