Memristor-Based Hardware Accelerator for Image Compression

Memristor-based hardware accelerators are gaining an increased attention as a potential candidate to speed-up the vector-matrix operations commonly needed in many digital image processing tasks due to their area, speed, and energy efficiency. In this paper, a memristor-based image compression (MR-IC) architecture that exploits a lossy 2-D discrete wavelet transform is proposed. The architecture is composed of a computational memristor crossbar, an intermediate memory array that stores the row-transformed coefficients and a final memory that holds the compressed version of the original image. The computational memristor array performs in-memory computation on the initially stored transformation coefficients. Using the quantitative analysis approach, we demonstrate a 10 × reduction in a number of operations compared with a conventional application-specific integrated circuit implementation. This translates to five orders of magnitude reduction in area, around 11 × improvement in energy efficiency, and 1.28 × speedup in computation time. Image quality metrics, such as peak signal-to-noise ratio (PSNR), structural similarity (SSIM) index, and complex wavelet-SSIM (CW-SSIM), are used to quantify the reduction in image quality due to lossy compression. The achieved metrics for conventional versus MR-IC are: PSNR 57.24 versus 33.29 dB, SSIM 0.9994 versus 0.8853, and CW-SSIM 1 versus 0.9983. Simulation results show that the 32 quantization levels proposed architecture provides significant improvements in energy, area, and performance compared to the 32 levels CMOS implementation with comparable CW-SSIM.