Memory accesses reordering for interconnect power reduction in sum-of-products computations

Konstantinos Masselos, Spyros Theoharis, Panagiotis Merakos, Thanos Stouraitis, Costas E. Goutis

Research output: Contribution to journalArticlepeer-review

4 Scopus citations


Techniques for interconnect power consumption reduction in realizations of sum-of-products computations are presented. The proposed techniques reorder the sequence of accesses of the coefficient and data memories to minimize power-costly address and data bus bit switching. The reordering problem is systematically formulated by mapping into the Traveling Salesman's Problem (TSP) for both single and multiple functional unit architectures. The cost function driving the memory accesses reordering procedure explicitly takes into consideration the static information related to algorithms' coefficients and storage addresses and data-related dynamic information. Experimental results from several typical digital signal-processing algorithms prove that the proposed techniques lead to significant bus switching activity savings. The power consumption in the data paths is reduced in most cases as well.

Original languageBritish English
Pages (from-to)2889-2899
Number of pages11
JournalIEEE Transactions on Signal Processing
Issue number11
StatePublished - Nov 2002


  • High-level synthesis
  • Interconnect
  • Low power
  • Memory
  • Sum-of-products


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