Abstract
A new approach is introduced that can be used to design families of systolic arrays that are better suited for the changing nature of real time applications. The proposed method integrates graph theoretic techniques for the design of systolic arrays with analysis tools to determine special algorithm realizations that are executable in a reduced number of cycles. The paper considers the design of smart arrays for matrix multiplication. These arrays have a limited reconfiguration that enables them to reduce compute time for a special class of matrices.
| Original language | British English |
|---|---|
| Pages (from-to) | 710-714 |
| Number of pages | 5 |
| Journal | Conference Record - Asilomar Conference on Circuits, Systems & Computers |
| Volume | 2 |
| State | Published - 1991 |
| Event | 24th Asilomar Conference on Signals, Systems and Computers Part 2 (of 2) - Pacific Grove, CA, USA Duration: 5 Nov 1990 → 7 Nov 1990 |