Matrix multiplication arrays with flexible compute time

A. O. Barbir, J. L. Aravena, H. Barada

Research output: Contribution to journalConference articlepeer-review


A new approach is introduced that can be used to design families of systolic arrays that are better suited for the changing nature of real time applications. The proposed method integrates graph theoretic techniques for the design of systolic arrays with analysis tools to determine special algorithm realizations that are executable in a reduced number of cycles. The paper considers the design of smart arrays for matrix multiplication. These arrays have a limited reconfiguration that enables them to reduce compute time for a special class of matrices.

Original languageBritish English
Pages (from-to)710-714
Number of pages5
JournalConference Record - Asilomar Conference on Circuits, Systems & Computers
StatePublished - 1991
Event24th Asilomar Conference on Signals, Systems and Computers Part 2 (of 2) - Pacific Grove, CA, USA
Duration: 5 Nov 19907 Nov 1990


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