@inproceedings{e9dea8a9fa314049877cc6f800093916,
title = "LPRE: Logarithmic Posit-enabled Reconfigurable edge-AI Engine",
abstract = "Edge-AI applications face huge challenges in resource-constrained environments, particularly in enhancing computational efficiency within bandwidth limitations. This work proposes the Logarithmic-Posit-enabled Reconfigurable edgeAI Engine (LPRE) that enhances hardware efficiency without compromising accuracy. The proposed architecture utilizes time-multiplexed dynamically configurable single-layer hardware to balance resource reuse and bandwidth for multi-layer perceptron and CNN models. Evaluations on LeNet-5 using MNIST demonstrate that LPRE achieves up to 4× throughput enhancement at 8-bit precision with negligible accuracy loss (compared to FP32 baseline), while requiring up to 80\% and 50\% fewer resources than fixed-point arithmetic and state-of-the-art works, respectively. The design is viable for various edge-AI applications, such as real-time number plate recognition, offering scalable, energy-efficient IoT solutions.",
keywords = "Edge-AI accelerators, Multi-layer perceptrons, Posit MAC, Quantization, Reconfigurable computing",
author = "Omkar Kokane and Mukul Lokhande and Gopal Raut and Adam Teman and Vishvakarma, \{Santosh Kumar\}",
note = "Publisher Copyright: {\textcopyright} 2025 IEEE.; 2025 IEEE International Symposium on Circuits and Systems, ISCAS 2025 ; Conference date: 25-05-2025 Through 28-05-2025",
year = "2025",
doi = "10.1109/ISCAS56072.2025.11043622",
language = "British English",
series = "Proceedings - IEEE International Symposium on Circuits and Systems",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "ISCAS 2025 - IEEE International Symposium on Circuits and Systems, Proceedings",
address = "United States",
}