## Abstract

In this paper, the potential of reducing power dissipation in a digital system using the Logarithmic Number System (LNS) is investigated. To provide a quantitative measure of power savings, the equivalence of an LNS to a linear fixed-point system is initially explored. The bit assertion activity of an LNS encoded signal is studied for both uniform and correlated Gaussian inputs. It is shown that LNS reduces the average bit assertion probability by more than 50%, in certain cases, over an equivalent linear representation. Finally, the impact of LNS on the hardware architecture and, by means of that, to power dissipation, is discussed. It is found that the average number of logic transitions is reduced by several times, for certain arithmetic operations and word lengths, thus compensating the power-dissipation overhead due to the unavoidable linear-to-logarithmic and logarithmic-tolinear conversion.

Original language | British English |
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Pages | 229-236 |

Number of pages | 8 |

State | Published - 2001 |

Event | 15th IEEE Symposium on Computer Arithmetic - Vail, CO, United States Duration: 11 Jun 2001 → 13 Jun 2001 |

### Conference

Conference | 15th IEEE Symposium on Computer Arithmetic |
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Country/Territory | United States |

City | Vail, CO |

Period | 11/06/01 → 13/06/01 |