## Abstract

A novel approach for the reduction of the power dissipated in a signal processing application is introduced in this paper. By exploiting the properties of the Polynomial Residue Number System (PRNS) and of the arithmetic modulo (2^{n} + 1), the power dissipation of implementing cyclic convolution is reduced up to four times. Furthermore, the corresponding power × delay product is reduced up to 2.4 times, while a simultaneous reduction of area cost is achieved. The particular performance improvement becomes possible by introducing a way to minimize the forward and inverse conversion overhead associated with PRNS. The introduced minimization exploits the fact that for the conversions for particular lengths of data sequences and particular moduli, only multiplications with powers of two and additions are required, thus leading to low implementation complexity.

Original language | British English |
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Pages (from-to) | 748-751 |

Number of pages | 4 |

Journal | Proceedings - IEEE International Symposium on Circuits and Systems |

Volume | 2 |

DOIs | |

State | Published - 2002 |