Low power architectures for digital signal processing

Konstantinos Masselos, Panagiotis Merakos, Thanos Stouraitis, Costas E. Goutis

Research output: Contribution to journalArticlepeer-review

1 Scopus citations


Low power architectures for digital signal processing algorithms requiring inner product computation are presented. In the first step a power efficient memory organization exploiting data reuse is determined. In the second step an order of evaluation of the partial products that reduces the switching activity at the inputs of the computational units is derived. Information related to both coefficients which are static and data which are dynamic, is used to drive the reordering of computation. Experimental results for several signal processing algorithms prove that the proposed techniques lead to significant savings in net switching activity and thus in power consumption.

Original languageBritish English
Pages (from-to)551-571
Number of pages21
JournalJournal of Systems Architecture
Issue number7
StatePublished - 3 Apr 2000


  • Computation reordering
  • Inner product computation
  • Low power
  • Switching activity


Dive into the research topics of 'Low power architectures for digital signal processing'. Together they form a unique fingerprint.

Cite this