Logarithmic number system for low-power arithmetic

V. Paliouras; T. Stouraitis

doi:10.1007/3-540-45373-3_30

Logarithmic number system for low-power arithmetic

V. Paliouras, T. Stouraitis

Electrical Engineering

University of Patras

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

25 Scopus citations

Abstract

In this paper, properties of the Logarithmic Number System (LNS) are investigated which can lead to power savings in a digital system. To quantitatively establish power savings, the equivalence of an LNS to a linear fixed-point system is, initially, explored and a related theorem is introduced. It is shown that LNS leads to reduction of the average bit assertion probability by more than 50%, in certain cases, over an equivalent linear representation. Finally, the impact of LNS on hardware architecture and, by means of that, to power dissipation, is discussed.

Original language	British English
Title of host publication	Integrated Circuit Design
Subtitle of host publication	Power and Timing Modeling, Optimization and Simulation - 10th International Workshop, PATMOS 2000, Proceedings
Editors	Dimitrios Soudris, Peter Pirsch, Erich Barke
Publisher	Springer Verlag
Pages	285-294
Number of pages	10
ISBN (Print)	9783540410683
DOIs	https://doi.org/10.1007/3-540-45373-3_30
State	Published - 2000
Event	10th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2000 - Gottingen, Germany Duration: 13 Sep 2000 → 15 Sep 2000

Publication series

Name	Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume	1918
ISSN (Print)	0302-9743
ISSN (Electronic)	1611-3349

Conference

Conference	10th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2000
Country/Territory	Germany
City	Gottingen
Period	13/09/00 → 15/09/00

Access to Document

10.1007/3-540-45373-3_30

Cite this

Paliouras, V., & Stouraitis, T. (2000). Logarithmic number system for low-power arithmetic. In D. Soudris, P. Pirsch, & E. Barke (Eds.), Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation - 10th International Workshop, PATMOS 2000, Proceedings (pp. 285-294). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 1918). Springer Verlag. https://doi.org/10.1007/3-540-45373-3_30

Paliouras, V. ; Stouraitis, T. / Logarithmic number system for low-power arithmetic. Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation - 10th International Workshop, PATMOS 2000, Proceedings. editor / Dimitrios Soudris ; Peter Pirsch ; Erich Barke. Springer Verlag, 2000. pp. 285-294 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)).

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abstract = "In this paper, properties of the Logarithmic Number System (LNS) are investigated which can lead to power savings in a digital system. To quantitatively establish power savings, the equivalence of an LNS to a linear fixed-point system is, initially, explored and a related theorem is introduced. It is shown that LNS leads to reduction of the average bit assertion probability by more than 50%, in certain cases, over an equivalent linear representation. Finally, the impact of LNS on hardware architecture and, by means of that, to power dissipation, is discussed.",

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Paliouras, V & Stouraitis, T 2000, Logarithmic number system for low-power arithmetic. in D Soudris, P Pirsch & E Barke (eds), Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation - 10th International Workshop, PATMOS 2000, Proceedings. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), vol. 1918, Springer Verlag, pp. 285-294, 10th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2000, Gottingen, Germany, 13/09/00. https://doi.org/10.1007/3-540-45373-3_30

Logarithmic number system for low-power arithmetic. / Paliouras, V.; Stouraitis, T.
Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation - 10th International Workshop, PATMOS 2000, Proceedings. ed. / Dimitrios Soudris; Peter Pirsch; Erich Barke. Springer Verlag, 2000. p. 285-294 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 1918).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - In this paper, properties of the Logarithmic Number System (LNS) are investigated which can lead to power savings in a digital system. To quantitatively establish power savings, the equivalence of an LNS to a linear fixed-point system is, initially, explored and a related theorem is introduced. It is shown that LNS leads to reduction of the average bit assertion probability by more than 50%, in certain cases, over an equivalent linear representation. Finally, the impact of LNS on hardware architecture and, by means of that, to power dissipation, is discussed.

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Paliouras V, Stouraitis T. Logarithmic number system for low-power arithmetic. In Soudris D, Pirsch P, Barke E, editors, Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation - 10th International Workshop, PATMOS 2000, Proceedings. Springer Verlag. 2000. p. 285-294. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)). doi: 10.1007/3-540-45373-3_30

Logarithmic number system for low-power arithmetic

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