Abstract
In this demo we will present DLD-VISU which is a web-based tool for the visualization and animation of digital logic design [1]. Combinatorial circuits can be built using logic gates, multiplexers, decoders, and look-up tables. Various configurations of finite state machines can be selected to define the machine type, the state code, and the flip-flop type. Logic minimization with the K-map approach and the Quine McCluskey scheme is also supported. The tools help students practice related topics in digital logic design courses. Also, instructors can use the tools to efficiently generate and verify examples for lecture notes or for homework problems and assignments. The tools support self-assessment and reflect the student learning process using learning curves. DLD-VISU, that was developed in collaboration between Khalifa University and Technische Universität Darmstadt, has been used in teaching digital logic design since Fall 2013 with a positive impact on students' motivation and learning.
| Original language | British English |
|---|---|
| Title of host publication | ISCAS 2016 - IEEE International Symposium on Circuits and Systems |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 1439 |
| Number of pages | 1 |
| ISBN (Electronic) | 9781479953400 |
| DOIs | |
| State | Published - 29 Jul 2016 |
| Event | 2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016 - Montreal, Canada Duration: 22 May 2016 → 25 May 2016 |
Publication series
| Name | Proceedings - IEEE International Symposium on Circuits and Systems |
|---|---|
| Volume | 2016-July |
| ISSN (Print) | 0271-4310 |
Conference
| Conference | 2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016 |
|---|---|
| Country/Territory | Canada |
| City | Montreal |
| Period | 22/05/16 → 25/05/16 |
UN SDGs
This output contributes to the following UN Sustainable Development Goals (SDGs)
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SDG 4 Quality Education
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