LDPC check node implementation using reversible logic

Muhammad Awais, Anas Razzaq, Ashfaq Ahmed, Guido Masera

Research output: Contribution to journalArticlepeer-review

8 Scopus citations

Abstract

Reversible logic is an emerging digital design paradigm which promises low energy dissipation; thanks to its information-lossless nature. True potential of this exciting concept can only be assessed by facing the design of practical complexity applications. Low density parity check (LDPC) decoding is one such application from forward error correction domain. The core of LDPC decoding is the check node (CN) processor, which executes the decoding algorithm and constitutes a major portion of decoder's overall power consumption. This work proposes a low-power LDPC CN architecture using reversible logic gates. Transistor level design and full custom layout of proposed architecture is carried out on UMC $90\, {\rm nm}$90nm complementary metal-oxide-semiconductor technology. All reversible blocks of proposed CN are optimised for quantum cost, garbage outputs and transistor count. The CN functionality is validated with post-layout simulations, layout versus schematic checks and design rule checks. The proposed CN occupies a post-layout area of 0.013mm2, achieves up to 4.3GHz frequency and consumes $52\, {\rm \mu W}$52μW power. The performance of proposed CN is also compared with its implementation using irreversible gates. The proposed CN achieves about 300% reduction in power delay product with affordable complexity as compared to its classical implementation.

Original languageBritish English
Pages (from-to)471-478
Number of pages8
JournalIET Circuits, Devices and Systems
Volume13
Issue number4
DOIs
StatePublished - 1 Jul 2019

Keywords

  • CMOS integrated circuits
  • decoding
  • forward error correction
  • logic circuits
  • logic design
  • logic gates
  • low-power electronics
  • parity check codes
  • transistors

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