Integration of thermal management and floorplanning based on three-dimensional layout representations

Three-dimensional integrated circuits hold great promise for performance improvement and power savings through the reduction of footprint and wire length. However, the technology comes with new challenges especially in the early design stages. One such challenge is the development and use of adequate floorplan representations. Another challenge is the accounting for thermal stress during the physical design stage of 3D integrated circuits. Contrasted with the conventional, layerwise 2D floorplanning approaches, genuine 3D layout representations naturally integrate vertical relations between layers. In this paper, we present a design flow that integrates 3D floorplanning with thermal awareness based on the use of native 3D layout representations. The floorplanning phase accounts for wirelength and chip area while the thermal verification phase use the insertion of thermal through silicon vias (TSVs) to reduce the number and magnitudes of hot spots. The main contribution of this paper is the integration of both phases within an iterative loop based on native 3D layout data structures. The impact of thermal TSV insertion strongly increases with the number of chip layers. We show that as little as 0.5% average TSV density can decrease the maximum chip temperature by 15, 45 and 90 degrees for two, three and four layer configurations of exemplary 3D designs, respectively. The presented approach paves the way for thermal-driven design methods that profit from the 3D representations of layouts made of several stacked layers.