Initialization for time delay digital tanlock loop

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

This paper presents an improved second-order time delay digital tanlock loop (TDTL) system. It uses an initialization technique to enhance some of the main performance parameters of the original TDTL loop and hence overcome some of the inherent loop limitations. A one-bit Sigma-Delta modulator is used to initialize the DCO (digital controlled oscillator) for coarse tuning mode in order to enhance the noise immunity of the TDTL loop. An evaluation of the improved architecture using Simulink/Matlab, under noise-free as well as noisy conditions, demonstrated marked improvements in performance compared to the original TDTL.

Original languageBritish English
Title of host publication2015 International Conference on Information and Communication Technology Research, ICTRC 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages108-111
Number of pages4
ISBN (Electronic)9781479989669
DOIs
StatePublished - 14 Jul 2015
Event1st International Conference on Information and Communication Technology Research, ICTRC 2015 - Abu Dhabi, United Arab Emirates
Duration: 17 May 201519 May 2015

Publication series

Name2015 International Conference on Information and Communication Technology Research, ICTRC 2015

Conference

Conference1st International Conference on Information and Communication Technology Research, ICTRC 2015
Country/TerritoryUnited Arab Emirates
CityAbu Dhabi
Period17/05/1519/05/15

Keywords

  • initialization
  • PLL
  • Sigma-delta

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