Improved performance second order time delay digital tanlock loop

S. R. Al-Araji, O. A. Al-Kharji Al-Ali, M. A. Al-Qutayri, N. A. Anani, P. Ponnapalli

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Scopus citations

Abstract

This paper presents a second order time delay digital tanlock loop with improved locking as well as acquisition performance. The former is achieved through replacement of the delay unit of the TDTL by a variable one whose phase error is controlled by the output of the phase detector. This approach maintains the quadrature relationship between the two TDTL channels and hence results in a linearized phase detector characteristics. Fast acquisition is obtained through modification of the free running sampling frequency of digital controlled oscillator (DCO) in order to speed up the loop digital filter response. This improved architecture was tested using various input signals including FSK (frequency shift keying) and the results show an enhanced performance when compared with the original TDTL system.

Original languageBritish English
Title of host publication33rd IEEE Sarnoff Symposium 2010, Conference Proceedings
DOIs
StatePublished - 2010
Event33rd IEEE Sarnoff Symposium 2010 - Princeton, NJ, United States
Duration: 12 Apr 201014 Apr 2010

Publication series

Name33rd IEEE Sarnoff Symposium 2010, Conference Proceedings

Conference

Conference33rd IEEE Sarnoff Symposium 2010
Country/TerritoryUnited States
CityPrinceton, NJ
Period12/04/1014/04/10

Keywords

  • Acquisition
  • FSK
  • Lock range
  • PLL
  • TDTL

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