Improved first-order time-delay tanlock loop architectures

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22 Scopus citations


This paper presents a study of the performance of the first-order time-delay digital tanlock loop (TDTL). It proposes a number of modified loop architectures that overcome some of the original TDTL design limitations. Simulation results indicate that the new architectures, which include delay switching, gain adaptation and a combination of both techniques, improve the TDTL performance in terms of acquisition speed, locking range and resilience to frequency disturbances. The first-order TDTL was also implemented on a field programmable gate array (FPGA). The real-time results from the FPGA implementation are in agreement with the ones obtained through simulation.

Original languageBritish English
Pages (from-to)1896-1908
Number of pages13
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Issue number9
StatePublished - Sep 2006


  • Architecture
  • Loop
  • Performance
  • Tanlock


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