Abstract
A new method is presented for complex multiplication. The method relies on encoding the complex numbers as seventh-order cyclic polynomials and viewing their product as an 8-point cyclic convolution. The result is that the complex multiplier is decomposed in multipliers of one fourth the wordlength of the original multiplier. These smaller multipliers are connected in a way forming a systolic array which performs the complex multiplication error free. The proposed decomposition can result in attractive VLSI implementations.
Original language | British English |
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Pages (from-to) | 923-927 |
Number of pages | 5 |
Journal | Conference Record - Asilomar Conference on Circuits, Systems & Computers |
Volume | 2 |
State | Published - 1991 |
Event | 24th Asilomar Conference on Signals, Systems and Computers Part 2 (of 2) - Pacific Grove, CA, USA Duration: 5 Nov 1990 → 7 Nov 1990 |