Implementation of reconfigurable time delay digital tanlock loop

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3 Scopus citations

Abstract

In this paper, a first order TDTL system is designed, simulated and implemented on a reconfigurable FPGA system. Initially the loop was designed and simulated using Matlab/Simulink. Subsequently some novel modifications were introduced to the TDTL in order to allow an optimized reconfigurable implementation, which eases the design process and allows for dynamic parameter and design modifications. The reconfigurable TDTL was tested in real time conditions under the same operating conditions of the simulated loop. Comparison between the simulated and real time results indicate a high degree of correlation, making the loop attractive for various practical applications.

Original languageBritish English
Article number14
Pages (from-to)110-117
Number of pages8
JournalProceedings of SPIE - The International Society for Optical Engineering
Volume5649
Issue numberPART 1
DOIs
StatePublished - 2005
EventSmart Structures, Devices, and Systems II - Sydney, Australia
Duration: 13 Dec 200415 Dec 2004

Keywords

  • Digital tanlock loop
  • Real-time
  • Reconfigurable
  • Time delay

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