Implementation of boost converter zero current detection using digital ASIC design flow

Maisam Wahbah; Baker Mohammad; Hani Saleh; Mohammed Ismail

doi:10.1109/ICECS.2014.7050082

Implementation of boost converter zero current detection using digital ASIC design flow

Maisam Wahbah
, Baker Mohammad
, Hani Saleh
, Mohammed Ismail

Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Energy can be harvested from ambient sources such as vibration, wireless, thermal and solar. Using energy harvesting in running ultra-low power systems could potentially enable battery-free operation in many applications, especially in wearable and implantable biomedicai devices. A special energy efficient interface circuit, which transfers harvested energy to be utilized by the load, is an essential part in the overall harvesting system. Traditionally, power converters such as DC-DC converters were entirely based on analog circuit design. This paper presents detailed implementation of a zero current detection technique for the inductor-based DC-DC converter using digital ASIC design flow. The proposed design was implemented using 65 nm Global Foundries Low Power CMOS process. It occupied an area of 209.88 μm² and consumed 8.07 μW. Furthermore, it ran at a frequency of 925.96 MHz. By using the ASIC design flow, the design is all-digital, portable and technology independent.

Original language	British English
Title of host publication	2014 21st IEEE International Conference on Electronics, Circuits and Systems, ICECS 2014
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	702-705
Number of pages	4
ISBN (Electronic)	9781479942428
DOIs	https://doi.org/10.1109/ICECS.2014.7050082
State	Published - 25 Feb 2015
Event	2014 21st IEEE International Conference on Electronics, Circuits and Systems, ICECS 2014 - Marseille, France Duration: 7 Dec 2014 → 10 Dec 2014

Publication series

Name	2014 21st IEEE International Conference on Electronics, Circuits and Systems, ICECS 2014

Conference

Conference	2014 21st IEEE International Conference on Electronics, Circuits and Systems, ICECS 2014
Country/Territory	France
City	Marseille
Period	7/12/14 → 10/12/14

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Keywords

65 nm
ASIC design flow
boost converter
standard-cell
Zero current detection

Access to Document

10.1109/ICECS.2014.7050082

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Wahbah, M., Mohammad, B., Saleh, H., & Ismail, M. (2015). Implementation of boost converter zero current detection using digital ASIC design flow. In 2014 21st IEEE International Conference on Electronics, Circuits and Systems, ICECS 2014 (pp. 702-705). Article 7050082 (2014 21st IEEE International Conference on Electronics, Circuits and Systems, ICECS 2014). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICECS.2014.7050082

Wahbah, Maisam ; Mohammad, Baker ; Saleh, Hani et al. / Implementation of boost converter zero current detection using digital ASIC design flow. 2014 21st IEEE International Conference on Electronics, Circuits and Systems, ICECS 2014. Institute of Electrical and Electronics Engineers Inc., 2015. pp. 702-705 (2014 21st IEEE International Conference on Electronics, Circuits and Systems, ICECS 2014).

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abstract = "Energy can be harvested from ambient sources such as vibration, wireless, thermal and solar. Using energy harvesting in running ultra-low power systems could potentially enable battery-free operation in many applications, especially in wearable and implantable biomedicai devices. A special energy efficient interface circuit, which transfers harvested energy to be utilized by the load, is an essential part in the overall harvesting system. Traditionally, power converters such as DC-DC converters were entirely based on analog circuit design. This paper presents detailed implementation of a zero current detection technique for the inductor-based DC-DC converter using digital ASIC design flow. The proposed design was implemented using 65 nm Global Foundries Low Power CMOS process. It occupied an area of 209.88 μm2 and consumed 8.07 μW. Furthermore, it ran at a frequency of 925.96 MHz. By using the ASIC design flow, the design is all-digital, portable and technology independent.",

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Wahbah, M, Mohammad, B , Saleh, H & Ismail, M 2015, Implementation of boost converter zero current detection using digital ASIC design flow. in 2014 21st IEEE International Conference on Electronics, Circuits and Systems, ICECS 2014., 7050082, 2014 21st IEEE International Conference on Electronics, Circuits and Systems, ICECS 2014, Institute of Electrical and Electronics Engineers Inc., pp. 702-705, 2014 21st IEEE International Conference on Electronics, Circuits and Systems, ICECS 2014, Marseille, France, 7/12/14. https://doi.org/10.1109/ICECS.2014.7050082

Implementation of boost converter zero current detection using digital ASIC design flow. / Wahbah, Maisam; Mohammad, Baker ; Saleh, Hani et al.
2014 21st IEEE International Conference on Electronics, Circuits and Systems, ICECS 2014. Institute of Electrical and Electronics Engineers Inc., 2015. p. 702-705 7050082 (2014 21st IEEE International Conference on Electronics, Circuits and Systems, ICECS 2014).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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Wahbah M, Mohammad B , Saleh H, Ismail M. Implementation of boost converter zero current detection using digital ASIC design flow. In 2014 21st IEEE International Conference on Electronics, Circuits and Systems, ICECS 2014. Institute of Electrical and Electronics Engineers Inc. 2015. p. 702-705. 7050082. (2014 21st IEEE International Conference on Electronics, Circuits and Systems, ICECS 2014). doi: 10.1109/ICECS.2014.7050082

Implementation of boost converter zero current detection using digital ASIC design flow

Abstract

Publication series

Conference

UN SDGs

Keywords

Access to Document

OpenUrl availability

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