Abstract
We describe a hybrid tool for hardware formal verification that links the HOL theorem prover and the MDG (Multiway Decision Graphs) model checker. Our tool supports abstract datatypes and uninterpreted function symbols available in MDG, allowing the verification of high level specifications. The hybrid tool, HOL-MDG, is based on an embedding in HOL of the grammar of the hardware modeling language, MDG-HDL, as well as an embedding of the first-order temporal logic ℒ mdg used to express properties for the MDG model checker. Verification with the hybrid tool is faster and more tractable than using either tools separately. We hence obtain the advantages of both verification paradigms.
Original language | British English |
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Pages | 392-395 |
Number of pages | 4 |
State | Published - 2004 |
Event | 16th International Conference on Microelectronics, ICM 2004 - Tunis, Tunisia Duration: 6 Dec 2004 → 8 Dec 2004 |
Conference
Conference | 16th International Conference on Microelectronics, ICM 2004 |
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Country/Territory | Tunisia |
City | Tunis |
Period | 6/12/04 → 8/12/04 |