Abstract
A combination of the signed digit (SD) and the logarithmic number system (LNS) for the creation of a hybrid SD/LNS processor is investigated. Appropriate radices were chosen for the SD system by taking into account both the speed of operations and the memory storage requirements. A new technique for high-speed conversion of SD to sign-magnitude numbers was developed to enhance the overall design. The hybrid SD/LNS processor exploits the parallelism that is offered by the SD number system to boost the performance of the fast LNS processors, and compares favourably to conventional LNS processor designs.
| Original language | British English |
|---|---|
| Pages (from-to) | 205-210 |
| Number of pages | 6 |
| Journal | IEE Proceedings E: Computers and Digital Techniques |
| Volume | 140 |
| Issue number | 4 |
| DOIs | |
| State | Published - 1993 |