Hybrid floating-point/logarithmic number system digital signal processor

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6 Scopus citations


The implementation of a novel hybrid floating-point processor is discussed. Additions are performed without any need for exponent alignment, and multiplications and divisions are performed in less time than that required for fixed-point additions. The processor is based on a combination of the logarithmic number system (LNS) representation with the signed digit (SD) representation. The SD number system offers parallelism at the digit level for the implementation of the various operations. A novel technique for parallel conversion of SD to sign-magnitude number is developed to enhance the overall design. The proposed processor compares favorably to previously developed hybrid floating-point processor designs. It is at least ten gate delays faster per addition/subtraction and eight gate delays faster per multiplication/division.

Original languageBritish English
Pages (from-to)1079-1082
Number of pages4
JournalICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings
StatePublished - 1989
Event1989 International Conference on Acoustics, Speech, and Signal Processing - Glasgow, Scotland
Duration: 23 May 198926 May 1989


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