High mobility Ge pMOS fabricated using a novel heteroepitaxial Ge on Si growth method

Ammar Nayfeh; Chi On Chui; Takao Yonehara; Krishna C. Saraswat

doi:10.1109/DRC.2005.1553069

High mobility Ge pMOS fabricated using a novel heteroepitaxial Ge on Si growth method

Ammar Nayfeh, Chi On Chui, Takao Yonehara, Krishna C. Saraswat

Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Using a novel multi-step in-situ growth and hydrogen annealing process heteroepitaxial-germanium layers have been grown directly on silicon, with defects confined near the Si/Ge interface, thus not threading to the surface as expected in this 4.2% lattice mismatched system. The results achieved are fully-relaxed single crystal Ge layers on Si with low density of x 10 ⁶ cm ^-2 without a graded buffer layer or CMP step. To demonstrate the quality of the Ge layers, pMOSFETs have been fabricated using a sub-500°C process with low field mobility of ∼250 cm ²/V-sec.

Original language	British English
Title of host publication	63rd Device Research Conference Digest, DRC'05
Pages	89-90
Number of pages	2
DOIs	https://doi.org/10.1109/DRC.2005.1553069
State	Published - 2005
Event	63rd Device Research Conference, DRC'05 - Santa Clara, CA, United States Duration: 20 Jun 2005 → 22 Jun 2005

Publication series

Name	Device Research Conference - Conference Digest, DRC
Volume	2005
ISSN (Print)	1548-3770

Conference

Conference	63rd Device Research Conference, DRC'05
Country/Territory	United States
City	Santa Clara, CA
Period	20/06/05 → 22/06/05

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10.1109/DRC.2005.1553069

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@inproceedings{e4916d32a4ec4f148eddcf4ce218053e,

title = "High mobility Ge pMOS fabricated using a novel heteroepitaxial Ge on Si growth method",

abstract = "Using a novel multi-step in-situ growth and hydrogen annealing process heteroepitaxial-germanium layers have been grown directly on silicon, with defects confined near the Si/Ge interface, thus not threading to the surface as expected in this 4.2% lattice mismatched system. The results achieved are fully-relaxed single crystal Ge layers on Si with low density of x 10 6 cm -2 without a graded buffer layer or CMP step. To demonstrate the quality of the Ge layers, pMOSFETs have been fabricated using a sub-500°C process with low field mobility of ∼250 cm 2/V-sec.",

author = "Ammar Nayfeh and Chui, {Chi On} and Takao Yonehara and Saraswat, {Krishna C.}",

year = "2005",

doi = "10.1109/DRC.2005.1553069",

language = "British English",

isbn = "0780390407",

series = "Device Research Conference - Conference Digest, DRC",

pages = "89--90",

booktitle = "63rd Device Research Conference Digest, DRC'05",

note = "63rd Device Research Conference, DRC'05 ; Conference date: 20-06-2005 Through 22-06-2005",

}

Nayfeh, A, Chui, CO, Yonehara, T & Saraswat, KC 2005, High mobility Ge pMOS fabricated using a novel heteroepitaxial Ge on Si growth method. in 63rd Device Research Conference Digest, DRC'05., 1553069, Device Research Conference - Conference Digest, DRC, vol. 2005, pp. 89-90, 63rd Device Research Conference, DRC'05, Santa Clara, CA, United States, 20/06/05. https://doi.org/10.1109/DRC.2005.1553069

High mobility Ge pMOS fabricated using a novel heteroepitaxial Ge on Si growth method. / Nayfeh, Ammar; Chui, Chi On; Yonehara, Takao et al.
63rd Device Research Conference Digest, DRC'05. 2005. p. 89-90 1553069 (Device Research Conference - Conference Digest, DRC; Vol. 2005).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - High mobility Ge pMOS fabricated using a novel heteroepitaxial Ge on Si growth method

AU - Nayfeh, Ammar

AU - Chui, Chi On

AU - Yonehara, Takao

AU - Saraswat, Krishna C.

PY - 2005

Y1 - 2005

N2 - Using a novel multi-step in-situ growth and hydrogen annealing process heteroepitaxial-germanium layers have been grown directly on silicon, with defects confined near the Si/Ge interface, thus not threading to the surface as expected in this 4.2% lattice mismatched system. The results achieved are fully-relaxed single crystal Ge layers on Si with low density of x 10 6 cm -2 without a graded buffer layer or CMP step. To demonstrate the quality of the Ge layers, pMOSFETs have been fabricated using a sub-500°C process with low field mobility of ∼250 cm 2/V-sec.

AB - Using a novel multi-step in-situ growth and hydrogen annealing process heteroepitaxial-germanium layers have been grown directly on silicon, with defects confined near the Si/Ge interface, thus not threading to the surface as expected in this 4.2% lattice mismatched system. The results achieved are fully-relaxed single crystal Ge layers on Si with low density of x 10 6 cm -2 without a graded buffer layer or CMP step. To demonstrate the quality of the Ge layers, pMOSFETs have been fabricated using a sub-500°C process with low field mobility of ∼250 cm 2/V-sec.

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U2 - 10.1109/DRC.2005.1553069

DO - 10.1109/DRC.2005.1553069

M3 - Conference contribution

AN - SCOPUS:33751325331

SN - 0780390407

SN - 9780780390409

T3 - Device Research Conference - Conference Digest, DRC

SP - 89

EP - 90

BT - 63rd Device Research Conference Digest, DRC'05

T2 - 63rd Device Research Conference, DRC'05

Y2 - 20 June 2005 through 22 June 2005

ER -

High mobility Ge pMOS fabricated using a novel heteroepitaxial Ge on Si growth method

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