Hardware/Software Co-acceleration of Progressive Learning under Feature Dimension Variation

In this paper, we address the problem of ASIC HW accelerator re-use in the case when the task-based feature set undergoes size changes. The proposed solution is a hybrid Hardware/Software (HW/SW) co-acceleration methodology for incorporating any additional features into the progressive learning model and performing inference without modifying the architecture of the HW accelerator. The co-acceleration methodology has been prototyped on an edge computing platform and compared with a HW-only acceleration in terms of inference throughput, compute resource utilization, and energy efficiency. The hybrid HW-SW co-accelerator is shown to result in a higher inference throughput while consuming less compute resources and energy than the HW-only solution. The results are further supported by using the HW accelerator's performance counters to profile overall performance under realistic progressive-learning workloads.