Hardware Speech Encryption Using a Chaotic Generator, Dynamic Shift and Bit Permutation

Mohammed F. Tolba, Wafaa S. Sayed, Ahmed G. Radwan, Salwa K. Abd-El-Hafiz, Ahmed M. Soliman

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    6 Scopus citations

    Abstract

    This paper proposes a speech encryption and decryption system, its hardware architecture design and FPGA implementation. The system utilizes Nosé Hoover chaotic generator and/or dynamic shift and bit permutation. The effect of different blocks in the proposed encryption scheme is studied and the security of the system is validated through perceptual and statistical tests. The complete encryption scheme is simulated using Xilinx ISE 14.5 and realized on FPGA Xilinx Kintex 7, presenting the experimental results on the oscilloscope. The efficiency is also validated through hardware resources utilization compared to previous works based on maximum frequency and throughput.

    Original languageBritish English
    Title of host publicationProceeding of 2018 30th International Conference on Microelectronics, ICM 2018
    PublisherInstitute of Electrical and Electronics Engineers Inc.
    Pages100-103
    Number of pages4
    ISBN (Electronic)9781538681671
    DOIs
    StatePublished - 2 Jul 2018
    Event30th International Conference on Microelectronics, ICM 2018 - Sousse, Tunisia
    Duration: 16 Dec 201819 Dec 2018

    Publication series

    NameProceedings of the International Conference on Microelectronics, ICM
    Volume2018-December

    Conference

    Conference30th International Conference on Microelectronics, ICM 2018
    Country/TerritoryTunisia
    CitySousse
    Period16/12/1819/12/18

    Keywords

    • Bit Permutation
    • Chaos
    • FPGA
    • Nosé Hoover
    • Speech Encryption

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