Hardware-Accelerated ZYNQ-NET Convolutional Neural Networks on Virtex-7 FPGA

Ahmed J.Abd El-Maksoud; Amr Gamal; Aya Hesham; Gamal Saied; Mennat Allah Ayman; Omnia Essam; Sara M. Mohamed; Eman El Mandouh; Ziad Ibrahim; Sara Mohamed; Hassan Mostafa

doi:10.1109/ICM52667.2021.9664956

Hardware-Accelerated ZYNQ-NET Convolutional Neural Networks on Virtex-7 FPGA

Ahmed J.Abd El-Maksoud, Amr Gamal, Aya Hesham, Gamal Saied, Mennat Allah Ayman, Omnia Essam, Sara M. Mohamed, Eman El Mandouh, Ziad Ibrahim, Sara Mohamed, Hassan Mostafa

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Convolutional neural network is a class of deep neural networks that has made a great breakthrough in image recognition. CNNs are commonly used to detect and classify visual applications so that they are frequently embedded in image classification tasks. The common trend nowadays is to accelerate the processing of CNNs in order to use them in real-time applications such as image classification and object recognition. This paper presents the implementation of ZynqNet CNN architecture on FPGA. The full ZynqNet CNN layers are implemented on FPGA to reach the max acceleration and make full use of all DSP units. Several optimizations techniques are used in different design phases to improve processing speed, utilized area, and power consumption. In addition, the proposed hardware accelerator achieves 15.6 fps for ZynqNet CNN at maximum frequency. The proposed architecture runs at two different frequencies of 100MHz and 125MHz, and is implemented on Virtex-7 FPGA.

Original language	British English
Title of host publication	2021 International Conference on Microelectronics, ICM 2021
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	70-73
Number of pages	4
ISBN (Electronic)	9781665408394
DOIs	https://doi.org/10.1109/ICM52667.2021.9664956
State	Published - 2021
Event	2021 International Conference on Microelectronics, ICM 2021 - New Cairo City, Egypt Duration: 19 Dec 2021 → 22 Dec 2021

Publication series

Name	Proceedings of the International Conference on Microelectronics, ICM

Conference

Conference	2021 International Conference on Microelectronics, ICM 2021
Country/Territory	Egypt
City	New Cairo City
Period	19/12/21 → 22/12/21

Keywords

Accelerating CNNs
Convolutional Neural Networks (CNNs)
FPGA
Hardware accelerators
ZynqNet

Access to Document

10.1109/ICM52667.2021.9664956

Cite this

El-Maksoud, A. J. A., Gamal, A., Hesham, A., Saied, G., Ayman, M. A., Essam, O., Mohamed, S. M., El Mandouh, E., Ibrahim, Z., Mohamed, S., & Mostafa, H. (2021). Hardware-Accelerated ZYNQ-NET Convolutional Neural Networks on Virtex-7 FPGA. In 2021 International Conference on Microelectronics, ICM 2021 (pp. 70-73). (Proceedings of the International Conference on Microelectronics, ICM). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICM52667.2021.9664956

@inproceedings{9010357953aa4986bc8ed4719ba0114c,

title = "Hardware-Accelerated ZYNQ-NET Convolutional Neural Networks on Virtex-7 FPGA",

abstract = "Convolutional neural network is a class of deep neural networks that has made a great breakthrough in image recognition. CNNs are commonly used to detect and classify visual applications so that they are frequently embedded in image classification tasks. The common trend nowadays is to accelerate the processing of CNNs in order to use them in real-time applications such as image classification and object recognition. This paper presents the implementation of ZynqNet CNN architecture on FPGA. The full ZynqNet CNN layers are implemented on FPGA to reach the max acceleration and make full use of all DSP units. Several optimizations techniques are used in different design phases to improve processing speed, utilized area, and power consumption. In addition, the proposed hardware accelerator achieves 15.6 fps for ZynqNet CNN at maximum frequency. The proposed architecture runs at two different frequencies of 100MHz and 125MHz, and is implemented on Virtex-7 FPGA.",

keywords = "Accelerating CNNs, Convolutional Neural Networks (CNNs), FPGA, Hardware accelerators, ZynqNet",

author = "El-Maksoud, {Ahmed J.Abd} and Amr Gamal and Aya Hesham and Gamal Saied and Ayman, {Mennat Allah} and Omnia Essam and Mohamed, {Sara M.} and {El Mandouh}, Eman and Ziad Ibrahim and Sara Mohamed and Hassan Mostafa",

note = "Funding Information: ACKNOWLEDGMENT This work was partially funded by ONE Lab at Zewail City of Science and Technology and Cairo University, Siemens EDA (Mentor Graphics), ASRT, NTRA, and ITAC Publisher Copyright: {\textcopyright} 2021 IEEE.; 2021 International Conference on Microelectronics, ICM 2021 ; Conference date: 19-12-2021 Through 22-12-2021",

year = "2021",

doi = "10.1109/ICM52667.2021.9664956",

language = "British English",

series = "Proceedings of the International Conference on Microelectronics, ICM",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "70--73",

booktitle = "2021 International Conference on Microelectronics, ICM 2021",

address = "United States",

}

El-Maksoud, AJA, Gamal, A, Hesham, A, Saied, G, Ayman, MA, Essam, O, Mohamed, SM, El Mandouh, E, Ibrahim, Z, Mohamed, S & Mostafa, H 2021, Hardware-Accelerated ZYNQ-NET Convolutional Neural Networks on Virtex-7 FPGA. in 2021 International Conference on Microelectronics, ICM 2021. Proceedings of the International Conference on Microelectronics, ICM, Institute of Electrical and Electronics Engineers Inc., pp. 70-73, 2021 International Conference on Microelectronics, ICM 2021, New Cairo City, Egypt, 19/12/21. https://doi.org/10.1109/ICM52667.2021.9664956

Hardware-Accelerated ZYNQ-NET Convolutional Neural Networks on Virtex-7 FPGA. / El-Maksoud, Ahmed J.Abd; Gamal, Amr; Hesham, Aya et al.
2021 International Conference on Microelectronics, ICM 2021. Institute of Electrical and Electronics Engineers Inc., 2021. p. 70-73 (Proceedings of the International Conference on Microelectronics, ICM).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Hardware-Accelerated ZYNQ-NET Convolutional Neural Networks on Virtex-7 FPGA

AU - El-Maksoud, Ahmed J.Abd

AU - Gamal, Amr

AU - Hesham, Aya

AU - Saied, Gamal

AU - Ayman, Mennat Allah

AU - Essam, Omnia

AU - Mohamed, Sara M.

AU - El Mandouh, Eman

AU - Ibrahim, Ziad

AU - Mohamed, Sara

AU - Mostafa, Hassan

N1 - Funding Information: ACKNOWLEDGMENT This work was partially funded by ONE Lab at Zewail City of Science and Technology and Cairo University, Siemens EDA (Mentor Graphics), ASRT, NTRA, and ITAC Publisher Copyright: © 2021 IEEE.

PY - 2021

Y1 - 2021

N2 - Convolutional neural network is a class of deep neural networks that has made a great breakthrough in image recognition. CNNs are commonly used to detect and classify visual applications so that they are frequently embedded in image classification tasks. The common trend nowadays is to accelerate the processing of CNNs in order to use them in real-time applications such as image classification and object recognition. This paper presents the implementation of ZynqNet CNN architecture on FPGA. The full ZynqNet CNN layers are implemented on FPGA to reach the max acceleration and make full use of all DSP units. Several optimizations techniques are used in different design phases to improve processing speed, utilized area, and power consumption. In addition, the proposed hardware accelerator achieves 15.6 fps for ZynqNet CNN at maximum frequency. The proposed architecture runs at two different frequencies of 100MHz and 125MHz, and is implemented on Virtex-7 FPGA.

AB - Convolutional neural network is a class of deep neural networks that has made a great breakthrough in image recognition. CNNs are commonly used to detect and classify visual applications so that they are frequently embedded in image classification tasks. The common trend nowadays is to accelerate the processing of CNNs in order to use them in real-time applications such as image classification and object recognition. This paper presents the implementation of ZynqNet CNN architecture on FPGA. The full ZynqNet CNN layers are implemented on FPGA to reach the max acceleration and make full use of all DSP units. Several optimizations techniques are used in different design phases to improve processing speed, utilized area, and power consumption. In addition, the proposed hardware accelerator achieves 15.6 fps for ZynqNet CNN at maximum frequency. The proposed architecture runs at two different frequencies of 100MHz and 125MHz, and is implemented on Virtex-7 FPGA.

KW - Accelerating CNNs

KW - Convolutional Neural Networks (CNNs)

KW - FPGA

KW - Hardware accelerators

KW - ZynqNet

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U2 - 10.1109/ICM52667.2021.9664956

DO - 10.1109/ICM52667.2021.9664956

M3 - Conference contribution

AN - SCOPUS:85124489294

T3 - Proceedings of the International Conference on Microelectronics, ICM

SP - 70

EP - 73

BT - 2021 International Conference on Microelectronics, ICM 2021

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2021 International Conference on Microelectronics, ICM 2021

Y2 - 19 December 2021 through 22 December 2021

ER -

El-Maksoud AJA, Gamal A, Hesham A, Saied G, Ayman MA, Essam O et al. Hardware-Accelerated ZYNQ-NET Convolutional Neural Networks on Virtex-7 FPGA. In 2021 International Conference on Microelectronics, ICM 2021. Institute of Electrical and Electronics Engineers Inc. 2021. p. 70-73. (Proceedings of the International Conference on Microelectronics, ICM). doi: 10.1109/ICM52667.2021.9664956

Hardware-Accelerated ZYNQ-NET Convolutional Neural Networks on Virtex-7 FPGA

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Keywords

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