Gradient-based optimization of custom circuits using a static-timing formulation

A. R. Conn, I. M. Elfadel, W. W. Molzen, P. R. O'Brien, P. N. Strenski, C. Visweswariah, C. B. Whan

Research output: Contribution to journalConference articlepeer-review

78 Scopus citations


This paper describes a method of optimally sizing digital circuits on a static-timing basis. All paths through the logic are considered simultaneously and no input patterns need be specified by the user. The method is unique in that it is based on gradient-based, nonlinear optimization and can accommodate transistor-level schematics without the need for pre-characterization. It employs efficient time-domain simulation and gradient computation for each channel-connected component. A large-scale, general-purpose, nonlinear optimization package is used to solve the tuning problem. A prototype tuner has been developed that accommodates combinational circuits consisting of parameterized library cells. Numerical results are presented.

Original languageBritish English
Pages (from-to)452-459
Number of pages8
JournalProceedings - Design Automation Conference
StatePublished - 1999
EventProceedings of the 1999 36th Annual Design Automation Conference (DAC) - New Orleans, LA, USA
Duration: 21 Jun 199925 Jun 1999


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