Ge based high performance nanoscale MOSFETs

It is believed that below the 65-nm node the conventional bulk CMOS can be scaled, however, without appreciable performance gains. To continue the scaling of Si CMOS in the sub-65nm regime, innovative device structures and new materials have to be created in order to continue the historic progress in information processing and transmission. Examples of novel device structures being investigated are double gate or surround gate MOS and examples of novel materials are high mobility channel materials like strained Si and Ge, high-k gate dielectrics and metal gate electrodes. Heterogeneous integration of these materials on Si with novel device structures may take us to sub-20 nm regime, but will require new fabrication technology solutions that are generally compatible with current and forecasted installed Si manufacturing.