TY - JOUR
T1 - Ge based high performance nanoscale MOSFETs
AU - Saraswat, Krishna C.
AU - Chui, Chi On
AU - Krishnamohan, Tejas
AU - Nayfeh, Ammar
AU - McIntyre, Paul
N1 - Funding Information:
This work was supported by DARPA, MARCO, Stanford CIS and NSF. Tejas Krishnamohan would like to thank Intel for providing a Fellowship. We would like to acknowledge Umicore for supplying the Ge wafers.
PY - 2005/6/17
Y1 - 2005/6/17
N2 - It is believed that below the 65-nm node the conventional bulk CMOS can be scaled, however, without appreciable performance gains. To continue the scaling of Si CMOS in the sub-65nm regime, innovative device structures and new materials have to be created in order to continue the historic progress in information processing and transmission. Examples of novel device structures being investigated are double gate or surround gate MOS and examples of novel materials are high mobility channel materials like strained Si and Ge, high-k gate dielectrics and metal gate electrodes. Heterogeneous integration of these materials on Si with novel device structures may take us to sub-20 nm regime, but will require new fabrication technology solutions that are generally compatible with current and forecasted installed Si manufacturing.
AB - It is believed that below the 65-nm node the conventional bulk CMOS can be scaled, however, without appreciable performance gains. To continue the scaling of Si CMOS in the sub-65nm regime, innovative device structures and new materials have to be created in order to continue the historic progress in information processing and transmission. Examples of novel device structures being investigated are double gate or surround gate MOS and examples of novel materials are high mobility channel materials like strained Si and Ge, high-k gate dielectrics and metal gate electrodes. Heterogeneous integration of these materials on Si with novel device structures may take us to sub-20 nm regime, but will require new fabrication technology solutions that are generally compatible with current and forecasted installed Si manufacturing.
KW - CMOS
KW - Germanium
KW - Heterostructure
KW - High-k dielectrics
UR - http://www.scopus.com/inward/record.url?scp=19944393250&partnerID=8YFLogxK
U2 - 10.1016/j.mee.2005.04.038
DO - 10.1016/j.mee.2005.04.038
M3 - Conference article
AN - SCOPUS:19944393250
SN - 0167-9317
VL - 80
SP - 15
EP - 21
JO - Microelectronic Engineering
JF - Microelectronic Engineering
IS - SUPPL.
T2 - 14th Biennial Conference on Insulating Films on Semiconductors
Y2 - 22 June 2005 through 24 June 2005
ER -