Fused floating-point arithmetic for DSP

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

17 Scopus citations

Abstract

This paper extends the consideration of fused floating-point arithmetic to operations that are frequently encountered in DSP. The Fast Fourier Transform is a case in point, it uses a complex butterfly operation. For a radix-2 implementation, the butterfly consists of a complex multiply followed by the complex addition and subtraction of the same pair of data. These butterfly operations can be implemented with two fused primitives, a fused two-term inner product and a fused add subtract unit. A floating-point fused FFT Butterfly unit is presented that performs single-precision butterfly floating-point operation in a time that is only 87% the time required for a conventional floating-point butterfly. When placed and routed in a 45nm process, the fused FFT Butterfly unit occupied about 72% of the area needed to implement a floating-point butterfly using conventional floating-point adders and multipliers. The numerical result of the fused butterfly unit is more accurate because fewer rounding operations are needed.

Original languageBritish English
Title of host publication2008 42nd Asilomar Conference on Signals, Systems and Computers, ASILOMAR 2008
Pages767-771
Number of pages5
DOIs
StatePublished - 2008
Event2008 42nd Asilomar Conference on Signals, Systems and Computers, ASILOMAR 2008 - Pacific Grove, CA, United States
Duration: 26 Oct 200829 Oct 2008

Publication series

NameConference Record - Asilomar Conference on Signals, Systems and Computers
ISSN (Print)1058-6393

Conference

Conference2008 42nd Asilomar Conference on Signals, Systems and Computers, ASILOMAR 2008
Country/TerritoryUnited States
CityPacific Grove, CA
Period26/10/0829/10/08

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