TY - GEN
T1 - Frequency synthesizer for wireless applications using TDTL
AU - Al-Humaidan, Abdulrahman
AU - Al-Araji, Saleh R.
AU - Al-Qutayri, Mahmoud
PY - 2006
Y1 - 2006
N2 - A frequency synthesizer using a first-order time delay tanlock loop (TDTL) is proposed in this work The synthesizer involves introducing an integer divider within the structure of the TDTL in order to produce multiple frequencies from one reference source, which in the case of the TDTL is the Digital Controlled Oscillator (DCO). An adaptive mechanism was embedded into the loop to compensate for the errors and changes the divider will cause when it is introduced within the loop for different division factors.
AB - A frequency synthesizer using a first-order time delay tanlock loop (TDTL) is proposed in this work The synthesizer involves introducing an integer divider within the structure of the TDTL in order to produce multiple frequencies from one reference source, which in the case of the TDTL is the Digital Controlled Oscillator (DCO). An adaptive mechanism was embedded into the loop to compensate for the errors and changes the divider will cause when it is introduced within the loop for different division factors.
UR - https://www.scopus.com/pages/publications/50249102722
U2 - 10.1109/APCCAS.2006.342511
DO - 10.1109/APCCAS.2006.342511
M3 - Conference contribution
AN - SCOPUS:50249102722
SN - 1424403871
SN - 9781424403875
T3 - IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS
SP - 1516
EP - 1519
BT - APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems
T2 - APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems
Y2 - 4 December 2006 through 6 December 2006
ER -