Fractional-order phase-locked loop

Reyad El-Khazali, Wajdi Ahmad

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

9 Scopus citations

Abstract

In this paper, a fractional-order analog phase-locked loop (FAPLL) model is proposed. In the new model, the traditional analog phase locked loop (APLL) is generalized by allowing the loop filters as well as the voltage controlled oscillators to acquire fractional order dynamics. The new model offers superior performance compared to its integer order counterpart in terms of capture and locking time response. The improvement realized in the response of the FAPLL outweighs the slight increase in the loop bandwidth, typically seen in fractional order systems. The main points of this work are illustrated via numerical examples.

Original languageBritish English
Title of host publication2007 9th International Symposium on Signal Processing and its Applications, ISSPA 2007, Proceedings
DOIs
StatePublished - 2007
Event2007 9th International Symposium on Signal Processing and its Applications, ISSPA 2007 - Sharjah, United Arab Emirates
Duration: 12 Feb 200715 Feb 2007

Publication series

Name2007 9th International Symposium on Signal Processing and its Applications, ISSPA 2007, Proceedings

Conference

Conference2007 9th International Symposium on Signal Processing and its Applications, ISSPA 2007
Country/TerritoryUnited Arab Emirates
CitySharjah
Period12/02/0715/02/07

Keywords

  • Fractional filters
  • Fractional order dynamics
  • Fractional voltage-controlled oscillator
  • Fractional-order PLL

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