Fractional-order digital phase-locked loop

Reyad El-Khazali

doi:10.1109/ICECS.2007.4511152

Fractional-order digital phase-locked loop

Reyad El-Khazali

Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

5 Scopus citations

Abstract

A fractional-order digital phase-locked loop (FODPLL) is proposed. The FODPLL model is developed by approximating a fractional-order digital controlled-oscillator (FODCO) with a finite dimensional discrete transfer function. The design of FODPLLs model is simplified where one only needs to design a FODCO. The FODPLL outperformed its integer order counterpart. The loop parameters will then be tuned to maintain stability and other design requirements. The main points of this work are illustrated via simple numerical example.

Original language	British English
Title of host publication	ICECS 2007 - 14th IEEE International Conference on Electronics, Circuits and Systems
Pages	963-966
Number of pages	4
DOIs	https://doi.org/10.1109/ICECS.2007.4511152
State	Published - 2007
Event	14th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2007 - Marrakech, Morocco Duration: 11 Dec 2007 → 14 Dec 2007

Publication series

Name	Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Conference

Conference	14th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2007
Country/Territory	Morocco
City	Marrakech
Period	11/12/07 → 14/12/07

Access to Document

10.1109/ICECS.2007.4511152

Cite this

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title = "Fractional-order digital phase-locked loop",

abstract = "A fractional-order digital phase-locked loop (FODPLL) is proposed. The FODPLL model is developed by approximating a fractional-order digital controlled-oscillator (FODCO) with a finite dimensional discrete transfer function. The design of FODPLLs model is simplified where one only needs to design a FODCO. The FODPLL outperformed its integer order counterpart. The loop parameters will then be tuned to maintain stability and other design requirements. The main points of this work are illustrated via simple numerical example.",

author = "Reyad El-Khazali",

year = "2007",

doi = "10.1109/ICECS.2007.4511152",

language = "British English",

isbn = "1424413788",

series = "Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems",

pages = "963--966",

booktitle = "ICECS 2007 - 14th IEEE International Conference on Electronics, Circuits and Systems",

note = "14th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2007 ; Conference date: 11-12-2007 Through 14-12-2007",

}

El-Khazali, R 2007, Fractional-order digital phase-locked loop. in ICECS 2007 - 14th IEEE International Conference on Electronics, Circuits and Systems., 4511152, Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, pp. 963-966, 14th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2007, Marrakech, Morocco, 11/12/07. https://doi.org/10.1109/ICECS.2007.4511152

Fractional-order digital phase-locked loop. / El-Khazali, Reyad.
ICECS 2007 - 14th IEEE International Conference on Electronics, Circuits and Systems. 2007. p. 963-966 4511152 (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - El-Khazali, Reyad

PY - 2007

Y1 - 2007

N2 - A fractional-order digital phase-locked loop (FODPLL) is proposed. The FODPLL model is developed by approximating a fractional-order digital controlled-oscillator (FODCO) with a finite dimensional discrete transfer function. The design of FODPLLs model is simplified where one only needs to design a FODCO. The FODPLL outperformed its integer order counterpart. The loop parameters will then be tuned to maintain stability and other design requirements. The main points of this work are illustrated via simple numerical example.

AB - A fractional-order digital phase-locked loop (FODPLL) is proposed. The FODPLL model is developed by approximating a fractional-order digital controlled-oscillator (FODCO) with a finite dimensional discrete transfer function. The design of FODPLLs model is simplified where one only needs to design a FODCO. The FODPLL outperformed its integer order counterpart. The loop parameters will then be tuned to maintain stability and other design requirements. The main points of this work are illustrated via simple numerical example.

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U2 - 10.1109/ICECS.2007.4511152

DO - 10.1109/ICECS.2007.4511152

M3 - Conference contribution

AN - SCOPUS:50649109612

SN - 1424413788

SN - 9781424413782

T3 - Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

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BT - ICECS 2007 - 14th IEEE International Conference on Electronics, Circuits and Systems

T2 - 14th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2007

Y2 - 11 December 2007 through 14 December 2007

ER -

Fractional-order digital phase-locked loop

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