FPGA realization of speech encryption based on modified chaotic logistic map

Mohammed F. Tolba; Wafaa S. Sayed; Ahmed G. Radwan; Salwa K. Abd-El-Hfiz

doi:10.1109/ICIT.2018.8352387

FPGA realization of speech encryption based on modified chaotic logistic map

Mohammed F. Tolba
, Wafaa S. Sayed
, Ahmed G. Radwan
, Salwa K. Abd-El-Hfiz

Nile University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

22 Scopus citations

Abstract

This paper presents an FPGA design and implementation of a chaotic speech encryption and decryption system based on bit permutations. Different encryption schemes are realized and compared. In addition, various testing methods including entropy, mean squared error, and correlation coefficients are used to analyze the efficiency of the system. The techniques for area and delay minimization are used. Carry look-ahead adder, multi-operand adder and booth multiplier are used to improve the performance of the encryption schemes design. A comparison between the different encryption architectures and the state of the art is introduced. The results demonstrate the good security of the proposed systems, which enables their utilization in speech telecommunication. The designs have been simulated using Xilinx ISE 14.7 and realized on FPGA Xilinx virtex-5 xc5lx50T. A throughput of 7.9 Gbit/sec for bit permutation design, 2.6 Gbit/sec for bit permutation and chaotic modified logistic map is achieved compared with 1.1 Gbit/sec and 1.49 Gbit/sec for previous work.

Original language	British English
Title of host publication	Proceedings - 2018 IEEE International Conference on Industrial Technology, ICIT 2018
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1412-1417
Number of pages	6
ISBN (Electronic)	9781509059492
DOIs	https://doi.org/10.1109/ICIT.2018.8352387
State	Published - 27 Apr 2018
Event	19th IEEE International Conference on Industrial Technology, ICIT 2018 - Lyon, France Duration: 19 Feb 2018 → 22 Feb 2018

Publication series

Name	Proceedings of the IEEE International Conference on Industrial Technology
Volume	2018-February

Conference

Conference	19th IEEE International Conference on Industrial Technology, ICIT 2018
Country/Territory	France
City	Lyon
Period	19/02/18 → 22/02/18

Keywords

Bit Permutation
Chaos
FPGA
Logistic map
Speech Encryption

Access to Document

10.1109/ICIT.2018.8352387

Cite this

Tolba, M. F., Sayed, W. S., Radwan, A. G., & Abd-El-Hfiz, S. K. (2018). FPGA realization of speech encryption based on modified chaotic logistic map. In Proceedings - 2018 IEEE International Conference on Industrial Technology, ICIT 2018 (pp. 1412-1417). (Proceedings of the IEEE International Conference on Industrial Technology; Vol. 2018-February). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICIT.2018.8352387

Tolba, Mohammed F. ; Sayed, Wafaa S. ; Radwan, Ahmed G. et al. / FPGA realization of speech encryption based on modified chaotic logistic map. Proceedings - 2018 IEEE International Conference on Industrial Technology, ICIT 2018. Institute of Electrical and Electronics Engineers Inc., 2018. pp. 1412-1417 (Proceedings of the IEEE International Conference on Industrial Technology).

@inproceedings{6b97c3656ab34083ae3c94b209aec7b5,

title = "FPGA realization of speech encryption based on modified chaotic logistic map",

abstract = "This paper presents an FPGA design and implementation of a chaotic speech encryption and decryption system based on bit permutations. Different encryption schemes are realized and compared. In addition, various testing methods including entropy, mean squared error, and correlation coefficients are used to analyze the efficiency of the system. The techniques for area and delay minimization are used. Carry look-ahead adder, multi-operand adder and booth multiplier are used to improve the performance of the encryption schemes design. A comparison between the different encryption architectures and the state of the art is introduced. The results demonstrate the good security of the proposed systems, which enables their utilization in speech telecommunication. The designs have been simulated using Xilinx ISE 14.7 and realized on FPGA Xilinx virtex-5 xc5lx50T. A throughput of 7.9 Gbit/sec for bit permutation design, 2.6 Gbit/sec for bit permutation and chaotic modified logistic map is achieved compared with 1.1 Gbit/sec and 1.49 Gbit/sec for previous work.",

keywords = "Bit Permutation, Chaos, FPGA, Logistic map, Speech Encryption",

author = "Tolba, \{Mohammed F.\} and Sayed, \{Wafaa S.\} and Radwan, \{Ahmed G.\} and Abd-El-Hfiz, \{Salwa K.\}",

note = "Funding Information: ACKNOWLEDGEMENT This research was supported financially by Cairo University, Egypt, research project no. 16-120. Publisher Copyright: {\textcopyright} 2018 IEEE.; 19th IEEE International Conference on Industrial Technology, ICIT 2018 ; Conference date: 19-02-2018 Through 22-02-2018",

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language = "British English",

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Tolba, MF, Sayed, WS, Radwan, AG & Abd-El-Hfiz, SK 2018, FPGA realization of speech encryption based on modified chaotic logistic map. in Proceedings - 2018 IEEE International Conference on Industrial Technology, ICIT 2018. Proceedings of the IEEE International Conference on Industrial Technology, vol. 2018-February, Institute of Electrical and Electronics Engineers Inc., pp. 1412-1417, 19th IEEE International Conference on Industrial Technology, ICIT 2018, Lyon, France, 19/02/18. https://doi.org/10.1109/ICIT.2018.8352387

FPGA realization of speech encryption based on modified chaotic logistic map. / Tolba, Mohammed F.; Sayed, Wafaa S.; Radwan, Ahmed G. et al.
Proceedings - 2018 IEEE International Conference on Industrial Technology, ICIT 2018. Institute of Electrical and Electronics Engineers Inc., 2018. p. 1412-1417 (Proceedings of the IEEE International Conference on Industrial Technology; Vol. 2018-February).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

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AU - Sayed, Wafaa S.

AU - Radwan, Ahmed G.

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PY - 2018/4/27

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N2 - This paper presents an FPGA design and implementation of a chaotic speech encryption and decryption system based on bit permutations. Different encryption schemes are realized and compared. In addition, various testing methods including entropy, mean squared error, and correlation coefficients are used to analyze the efficiency of the system. The techniques for area and delay minimization are used. Carry look-ahead adder, multi-operand adder and booth multiplier are used to improve the performance of the encryption schemes design. A comparison between the different encryption architectures and the state of the art is introduced. The results demonstrate the good security of the proposed systems, which enables their utilization in speech telecommunication. The designs have been simulated using Xilinx ISE 14.7 and realized on FPGA Xilinx virtex-5 xc5lx50T. A throughput of 7.9 Gbit/sec for bit permutation design, 2.6 Gbit/sec for bit permutation and chaotic modified logistic map is achieved compared with 1.1 Gbit/sec and 1.49 Gbit/sec for previous work.

AB - This paper presents an FPGA design and implementation of a chaotic speech encryption and decryption system based on bit permutations. Different encryption schemes are realized and compared. In addition, various testing methods including entropy, mean squared error, and correlation coefficients are used to analyze the efficiency of the system. The techniques for area and delay minimization are used. Carry look-ahead adder, multi-operand adder and booth multiplier are used to improve the performance of the encryption schemes design. A comparison between the different encryption architectures and the state of the art is introduced. The results demonstrate the good security of the proposed systems, which enables their utilization in speech telecommunication. The designs have been simulated using Xilinx ISE 14.7 and realized on FPGA Xilinx virtex-5 xc5lx50T. A throughput of 7.9 Gbit/sec for bit permutation design, 2.6 Gbit/sec for bit permutation and chaotic modified logistic map is achieved compared with 1.1 Gbit/sec and 1.49 Gbit/sec for previous work.

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Tolba MF, Sayed WS, Radwan AG, Abd-El-Hfiz SK. FPGA realization of speech encryption based on modified chaotic logistic map. In Proceedings - 2018 IEEE International Conference on Industrial Technology, ICIT 2018. Institute of Electrical and Electronics Engineers Inc. 2018. p. 1412-1417. (Proceedings of the IEEE International Conference on Industrial Technology). doi: 10.1109/ICIT.2018.8352387

FPGA realization of speech encryption based on modified chaotic logistic map

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