@inproceedings{3c98297019ee475aa0749e078f7be4a5,
title = "FPGA realization of Caputo and Gr{\"u}nwald-Letnikov operators",
abstract = "This paper proposes a hardware platform implementation on FPGA for two fractional-order derivative operators. The Gr{\"u}nwald-Letnikov and Caputo definitions are realized for different fractional orders. The realization is based on non-uniform segmentation algorithm with a variable lookup table. A generic implementation for Gr{\"u}nwald-Letnikov is proposed and a 32 bit Fixed Point Booth multiplier radix-4 is used for Caputo implementation. Carry look-ahead adder, multi-operand adder and booth multiplier are used to improve the performance and other techniques for area and delay minimization have been employed. A comparison between the two presented architectures is introduced. The proposed designs have been simulated using Xilinx ISE and realized on FPGA Xilinx virtex-5 XC5VLX50T. The total area of 2515 look up tables is achieved for Caputo implementation, and maximum frequency of 54.11 MHz and 1498 slices are achieved for Gr{\"u}nwald-Letnikov architecture.",
keywords = "Caputo, FPGA, Fractional calculus, Gr{\"u}nwald-Letnikov, LUT, Non-uniform segmentation",
author = "Tolba, {Mohammed F.} and Abdelaty, {Amr M.} and Said, {Lobna A.} and Elwakil, {Ahmed S.} and Azar, {Ahmad Taher} and Madian, {Ahmed H.} and Adel Ounnas and Radwan, {Ahmed G.}",
note = "Publisher Copyright: {\textcopyright} 2017 IEEE.; 6th International Conference on Modern Circuits and Systems Technologies, MOCAST 2017 ; Conference date: 04-05-2017 Through 06-05-2017",
year = "2017",
month = may,
day = "31",
doi = "10.1109/MOCAST.2017.7937659",
language = "British English",
series = "2017 6th International Conference on Modern Circuits and Systems Technologies, MOCAST 2017",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2017 6th International Conference on Modern Circuits and Systems Technologies, MOCAST 2017",
address = "United States",
}