FPGA-based hash circuit synthesis with evolutionary algorithms

Ernesto Damiani, Valentino Liberali, Andrea G.B. Tettamanzi

Research output: Contribution to journalArticlepeer-review

1 Scopus citations

Abstract

An evolutionary algorithm is used to evolve a digital circuit which computes a simple hash function mapping a 16-bit address space into an 8-bit one. The target technology is FPGA, where the search space of the algorithm is made of the combinational functions computed by cells and of the interconnections among cells. The evolutionary technique has been applied to five different interconnection topologies, specified by neighbourhood graphs. This, circuit is readily applicable to the design of set-associative cache memories. Possible use of the evolutionary approach presented in the paper for on-line tuning of the function during cache operation is also discussed.

Original languageBritish English
Pages (from-to)1888-1896
Number of pages9
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
VolumeE82-A
Issue number9
StatePublished - 1999

Keywords

  • Evolutionary algorithms
  • Evolvable hardware
  • FPGA
  • Non-linear circuit synthesis

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