Abstract
This paper describes two fused floating-point operations and applies them to the implementation of fast Fourier transform (FFT) processors. The fused operations are a two-term dot product and an add-subtract unit. The FFT processors use "butterfly" operations that consist of multiplications, additions, and subtractions of complex valued data. Both radix-2 and radix-4 butterflies are implemented efficiently with the two fused floating-point operations. When placed and routed using a high performance standard cell technology, the fused FFT butterflies are about 15 percent faster and 30 percent smaller than a conventional implementation. Also the numerical results of the fused implementations are slightly more accurate, since they use fewer rounding operations.
Original language | British English |
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Article number | 5669293 |
Pages (from-to) | 284-288 |
Number of pages | 5 |
Journal | IEEE Transactions on Computers |
Volume | 61 |
Issue number | 2 |
DOIs | |
State | Published - 2012 |
Keywords
- fast Fourier transform
- Floating-point arithmetic
- fused floating-point operations
- Radix-2 FFT butterfly
- Radix-4 FFT butterfly