Establishing a lower bound on systolic execution time

H. Barada, A. El-Amawy

Research output: Contribution to conferencePaperpeer-review

Abstract

A tool called the Systolic Precedence Diagram (SPD), for use in the systematic mapping of compute-bound algorithms into time-optimal systolic architectures, is presented. The SPD graphically displays the computations in accordance with the algorithmic precedence rules under the systolic requirements. It provides a model from which parallel operations are identified and establishes a lower bound on the systolic execution time of an algorithm.

Original languageBritish English
Pages216-220
Number of pages5
StatePublished - Mar 1989
EventProceedings: the Twenty-First Southeastern Symposium on System Theory - Tallahassee, FL, USA
Duration: 26 Mar 198928 Mar 1989

Conference

ConferenceProceedings: the Twenty-First Southeastern Symposium on System Theory
CityTallahassee, FL, USA
Period26/03/8928/03/89

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