Enhancing Circuit Authentication through Secure Isolation

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

Outsourcing chip production is common among semiconductor vendors to cope with the increasing demand for integrated circuits. This has resulted in several security issues in the chip supply chain, including hardware trojans, intellectual property theft, and overproduction. The concept of zero trust -never trust, always verify- presents a promising solution for ensuring the authenticity of Integrated Circuits (ICs), particularly in critical systems where adversary attacks can cause significant losses or damage. The Security Protocol and Data Model (SPDM) is a reliable protocol that uses certificates to ensure the authenticity of ICs. Based on this protocol, the presented paper proposes a chip-to-chip zero-trust security architecture that aims to verify the authenticity of any connected peripheral before its use. The contributions include an overview of the proposed architecture, the anti-clock stretching technique, and an analysis of the challenges encountered during the implementation and execution.

Original languageBritish English
Title of host publicationISCAS 2024 - IEEE International Symposium on Circuits and Systems
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9798350330991
DOIs
StatePublished - 2024
Event2024 IEEE International Symposium on Circuits and Systems, ISCAS 2024 - Singapore, Singapore
Duration: 19 May 202422 May 2024

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310

Conference

Conference2024 IEEE International Symposium on Circuits and Systems, ISCAS 2024
Country/TerritorySingapore
CitySingapore
Period19/05/2422/05/24

Keywords

  • Chip-to-Chip
  • Clock-stretching
  • Hardware security
  • SPDM
  • Zero Trust

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