Abstract
In this work, the fabrication of charge trapping memory cells with laser-synthesized indium-nitride nanoparticles (InN-NPs) embedded in ZnO charge trapping layer is demonstrated. Atomic layer deposited A1203 layers are used as tunnel and blocking oxides. The gate contacts are sputtered using a shadow mask which eliminates the need for any lithography steps. High frequency C-Vgate measurements show that a memory effect is observed, due to the charging of the InN-NPs. With a low operating voltage of 4 V, the memory shows a noticeable threshold voltage (V,) shift of 2 V, which indicates that InN-NPs act as charge trapping centers. Without InN-NPs, the observed memory hysteresis is negligible. At higher programming voltages of 10 V, a memory window of 5 V is achieved and the V, shift direction indicates that electrons tunnel from channel to charge storage layer.
| Original language | British English |
|---|---|
| Article number | 253106 |
| Journal | Applied Physics Letters |
| Volume | 104 |
| Issue number | 25 |
| DOIs | |
| State | Published - 23 Jun 2014 |
UN SDGs
This output contributes to the following UN Sustainable Development Goals (SDGs)
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SDG 7 Affordable and Clean Energy
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