@inbook{58d81a219a7e4ceeb006cb86f899cc35,
title = "Embedded Memory Verification",
abstract = "Verification of integrated circuits is a complex task that attempts to assure that the design performs correctly under all combinations and cases. Since the combinations of internal states and input for any design force designer to endure an all-consuming, exhaustive simulation, due to the tediously large amount of combinations, optimized algorithm is implied to encompass as much coverage as possible.",
keywords = "Automatic Test Pattern Generation, Gate Level, Level Verification, SRAM Cell, Transistor Level",
author = "Baker Mohammad",
note = "Publisher Copyright: {\textcopyright} 2014, Springer Science+Business Media New York.",
year = "2014",
doi = "10.1007/978-1-4614-8881-1_7",
language = "British English",
series = "Analog Circuits and Signal Processing",
publisher = "Springer",
pages = "69--74",
booktitle = "Analog Circuits and Signal Processing",
address = "Germany",
}