Embedded memory interface logic and interconnect testing

Research output: Contribution to journalArticlepeer-review

7 Scopus citations

Abstract

The increased size of embedded memory for system-on-chip (SoC) and multicore processors has a positive impact on performance yet poses a big challenge for chip yield, power consumption, and overall cost. Big percentage (>60%) of today's processors and SoC area in both 2-D (planar) and 3-D technologies, such as through silicon via (TSV), are dedicated to memory. Most of today's embedded memories are not as simple as a storage area with single interface of data, address, and control, but rather they compromise complex logic on their interface due to timing constrains and interconnect technologies (NoC and TSV). Memory core testing strategy is well understood and has mature tools and methodologies to screen for defects such as built-in-self-test (BIST). In addition, core and logic-based testing using scan and automatic test pattern generation (ATPG) tools and methodologies are intended for flop-based design. However, interface logic and complex interconnect like the one in 3-D chips are not thoroughly tested using BIST or ATPG as they are not designed for such logic. This becomes even more important for 3-D chips where a stack memory could have different testing strategies other than the base layer core which is interfacing with it. This brief presents a design for test methodology to achieve good coverage on interface logic for embedded and stack memory. The proposed approach uses modified ATPG and scan methodology to test the memory logic interface with minimum impact to existing design.

Original languageBritish English
Article number6898035
Pages (from-to)1946-1950
Number of pages5
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume23
Issue number9
DOIs
StatePublished - 1 Sep 2015

Keywords

  • 3-D testing
  • automatic test pattern generation (ATPG)
  • design for test (DFT)
  • embedded memory
  • yield

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