Embedded Memory Hierarchy

Research output: Chapter in Book/Report/Conference proceedingChapterpeer-review


As was shown in Chap. 2 there are many levels of embedded memory and caches. The reason for splitting into multiple levels is to tradeoff between speed and capacity [35, 54]. The smaller the size the faster the access time is. This is true because there is less entry to search through and there is less area for signal to propagate to the execution unites. In addition, the number of multiplexer to select the data is less for smaller memory size. Bigger memory size tends to use smaller SRAM cell size because the emphasis is more on density rather than speed, which also contribute to longer access time.

Original languageBritish English
Title of host publicationAnalog Circuits and Signal Processing
Number of pages7
StatePublished - 2014

Publication series

NameAnalog Circuits and Signal Processing
ISSN (Print)1872-082X
ISSN (Electronic)2197-1854


  • Access Time
  • Cache Line
  • Leakage Power
  • Memory Hierarchy
  • Memory Size


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