@inbook{37c5b242301d4ffb91eec5f7d47d9c81,
title = "Embedded Memory Hierarchy",
abstract = "As was shown in Chap. 2 there are many levels of embedded memory and caches. The reason for splitting into multiple levels is to tradeoff between speed and capacity [35, 54]. The smaller the size the faster the access time is. This is true because there is less entry to search through and there is less area for signal to propagate to the execution unites. In addition, the number of multiplexer to select the data is less for smaller memory size. Bigger memory size tends to use smaller SRAM cell size because the emphasis is more on density rather than speed, which also contribute to longer access time.",
keywords = "Access Time, Cache Line, Leakage Power, Memory Hierarchy, Memory Size",
author = "Baker Mohammad",
note = "Publisher Copyright: {\textcopyright} 2014, Springer Science+Business Media New York.",
year = "2014",
doi = "10.1007/978-1-4614-8881-1_3",
language = "British English",
series = "Analog Circuits and Signal Processing",
publisher = "Springer",
pages = "29--35",
booktitle = "Analog Circuits and Signal Processing",
address = "Germany",
}