Embedded Memory Design Validation and Design For Test

Research output: Chapter in Book/Report/Conference proceedingChapterpeer-review

1 Scopus citations


Design verification and design for test go hand-in-hand because of the close interactions between the two. There is a tradeoff between the overhead of making a design correctly by construction or through extensive verification for logic and circuit in terms of power, area, cost, and speed. The end goal of any design is to have a competitive product that meets market goals in terms of performance, power, cost, and time to market. Chapter 4 discussed in detail the impact of process variation on circuit performance and how it affects product yield; design verification and design testing are two important steps in design cycle that aim to get a functional design with high yield. The difference between verification and testing (validation) is that verification is done pre-fabrication, using different levels of design abstraction, while silicon validation is post-fabrication. For example, the first level of verification uses a verilog view of the memory and focuses on functionality and logic correctness using CAD tools, while gate level verification uses gate level view with some abstraction for memory cell to verify timing constraints in addition to basic functionality. Chapter 7 discussed verification part in details and this chapter is focusing on design for test and silicon validation.

Original languageBritish English
Title of host publicationAnalog Circuits and Signal Processing
Number of pages7
StatePublished - 2014

Publication series

NameAnalog Circuits and Signal Processing
ISSN (Print)1872-082X
ISSN (Electronic)2197-1854


  • Affect Product Yield
  • Built-in Self-test (BIST)
  • Gate-level Verification
  • Silicon Validation
  • Verify Timing Constraints


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