Electret-Free electrostatic energy harvesting interface circuit design and analysis

Lilas Al-Rahis, Baker Mohammed, Hani Saleh, Mohammad Ismail

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

In this paper, electrostatic energy harvesting interface circuit is introduced and analyzed. The harvester and interface circuit are designed using GF 65nm process technology and cadence CAD tools. System level analysis is performed where the impact of the initial voltage level and the harvester resonance frequency have been studied. Moreover, the maximum power that can be delivered to a resistive load using the harvester is presented. The efficiency of the interface circuit was shown to increase with higher resonance frequencies and initial voltage levels. As a result, however, the output voltage achieved by the harvesters was shown to exceed the tolerable voltage by CMOS technology. The proposed design includes a reconfigurable switch capacitor to reduce the electrostatic energy harvesting circuit voltage from 3V to 1.5V.

Original languageBritish English
Title of host publication2016 IEEE 59th International Midwest Symposium on Circuits and Systems, MWSCAS 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781509009169
DOIs
StatePublished - 2 Mar 2017
Event59th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2016 - Abu Dhabi, United Arab Emirates
Duration: 16 Oct 201619 Oct 2016

Publication series

NameMidwest Symposium on Circuits and Systems
ISSN (Print)1548-3746

Conference

Conference59th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2016
Country/TerritoryUnited Arab Emirates
CityAbu Dhabi
Period16/10/1619/10/16

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