Efficient VLSI implementation of logarithmic signal processors

Research output: Contribution to journalConference articlepeer-review


A hybrid logarithmic processor based on the logarithmic number system (LNS) is introduced. The LNS exponents of the operands are represented internally using the signed-digit (SD) number system. The LNS exponents, represented traditionally as fixed-point or sign-magnitude numbers, are converted to an SD format and then processed. This allows the parallelism offered by the SD number system at the digital level to be exploited for the implementation of the various operations. In order to reduce the size of the memory tables required for LNS operations like addition and subtraction, a technique for parallel conversion of SD to sign-magnitude numbers is developed. The new processor compares favorably to a previously developed logarithmic processor in terms of computational speed. It also results a more regular and modular VLSI implementation.

Original languageBritish English
Pages (from-to)1540-1543
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
StatePublished - 1989
EventIEEE International Symposium on Circuits and Systems 1989, the 22nd ISCAS. Part 1 - Portland, OR, USA
Duration: 8 May 198911 May 1989


Dive into the research topics of 'Efficient VLSI implementation of logarithmic signal processors'. Together they form a unique fingerprint.

Cite this