Efficient low-power bus architecture

A. Rjoub; S. Nikolaidis; O. Koufopavlou; T. Stouraitis

Efficient low-power bus architecture

A. Rjoub, S. Nikolaidis, O. Koufopavlou, T. Stouraitis

Electrical Engineering

University of Patras

Research output: Contribution to journal › Conference article › peer-review

6 Scopus citations

Abstract

In this paper a new low power bus architecture based on the reduced voltage swing technique, is proposed. A driver circuit and a receiver are designed using strictly simple design principles and conventional CMOS technology. A considerable reduction in power consumption is achieved. The influence of the swing level on the time performance is also examined. The same architecture with a new repeater circuit is used, for driving internal long interconnection lines and similar results are obtained.

Original language	British English
Pages (from-to)	1864-1867
Number of pages	4
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	3
State	Published - 1997
Event	Proceedings of the 1997 IEEE International Symposium on Circuits and Systems, ISCAS'97. Part 4 (of 4) - Hong Kong, Hong Kong Duration: 9 Jun 1997 → 12 Jun 1997

Cite this

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title = "Efficient low-power bus architecture",

abstract = "In this paper a new low power bus architecture based on the reduced voltage swing technique, is proposed. A driver circuit and a receiver are designed using strictly simple design principles and conventional CMOS technology. A considerable reduction in power consumption is achieved. The influence of the swing level on the time performance is also examined. The same architecture with a new repeater circuit is used, for driving internal long interconnection lines and similar results are obtained.",

author = "A. Rjoub and S. Nikolaidis and O. Koufopavlou and T. Stouraitis",

year = "1997",

language = "British English",

volume = "3",

pages = "1864--1867",

journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

issn = "0271-4310",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "Proceedings of the 1997 IEEE International Symposium on Circuits and Systems, ISCAS'97. Part 4 (of 4) ; Conference date: 09-06-1997 Through 12-06-1997",

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TY - JOUR

T1 - Efficient low-power bus architecture

AU - Rjoub, A.

AU - Nikolaidis, S.

AU - Koufopavlou, O.

AU - Stouraitis, T.

PY - 1997

Y1 - 1997

N2 - In this paper a new low power bus architecture based on the reduced voltage swing technique, is proposed. A driver circuit and a receiver are designed using strictly simple design principles and conventional CMOS technology. A considerable reduction in power consumption is achieved. The influence of the swing level on the time performance is also examined. The same architecture with a new repeater circuit is used, for driving internal long interconnection lines and similar results are obtained.

AB - In this paper a new low power bus architecture based on the reduced voltage swing technique, is proposed. A driver circuit and a receiver are designed using strictly simple design principles and conventional CMOS technology. A considerable reduction in power consumption is achieved. The influence of the swing level on the time performance is also examined. The same architecture with a new repeater circuit is used, for driving internal long interconnection lines and similar results are obtained.

UR - http://www.scopus.com/inward/record.url?scp=0030715210&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:0030715210

SN - 0271-4310

VL - 3

SP - 1864

EP - 1867

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

T2 - Proceedings of the 1997 IEEE International Symposium on Circuits and Systems, ISCAS'97. Part 4 (of 4)

Y2 - 9 June 1997 through 12 June 1997

ER -

Efficient low-power bus architecture

Abstract

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