Efficient low-power bus architecture

A. Rjoub, S. Nikolaidis, O. Koufopavlou, T. Stouraitis

Research output: Contribution to journalConference articlepeer-review

6 Scopus citations


In this paper a new low power bus architecture based on the reduced voltage swing technique, is proposed. A driver circuit and a receiver are designed using strictly simple design principles and conventional CMOS technology. A considerable reduction in power consumption is achieved. The influence of the swing level on the time performance is also examined. The same architecture with a new repeater circuit is used, for driving internal long interconnection lines and similar results are obtained.

Original languageBritish English
Pages (from-to)1864-1867
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
StatePublished - 1997
EventProceedings of the 1997 IEEE International Symposium on Circuits and Systems, ISCAS'97. Part 4 (of 4) - Hong Kong, Hong Kong
Duration: 9 Jun 199712 Jun 1997


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